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1 ? x9401 low noise/low power/spi bus quad, 64 tap, digitally controlled potentiometer (xdcp?) description the x9401 integrates 4 digita lly controlled potentiometers (xdcp) on a monolithic cmos integrated microcircuit. the digitally controlled potentio meter is implemented using 64 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. each potentiometer has associated with it a volatile wiper counter register (wcr) and 4 nonvolatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array through the switches. power-up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? quad - 4 separate pots, 64 taps/pot ? nonvolatile storage of wiper position ? four nonvolatile data registers for each pot ? 16-bytes of eeprom memory ? spi serial interface ?r total = 10k ? wiper resistance = 150 typical ? standby current < 3a (total package) ? operating current < 700a max. ?v cc = 2.7v to 5v ? 24 ld soic and 24 ld tssop package ? 100 year data retention ? pb-free available (rohs compliant) block diagram interface and control circuitry cs sck so a0 a1 r0 r1 r2 r3 wiper counter register (wcr) resistor array pot 1 v h1 /r h1 v l1 /r l1 r0 r1 r2 r3 wiper counter register (wcr) v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 r0 r1 r2 r3 resistor array v h2 /r h2 v l2 /r l2 v w2 /r w2 r0 r1 r2 r3 resistor array v h3 /r h3 v l3 /r l3 v w3 /r w3 wiper counter register (wcr) wiper counter register (wcr) pot 3 pot 2 hold pot 0 v cc v ss wp si caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005-2006, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. data sheet fn8190.4 october 13, 2009
2 fn8190.4 october 13, 2009 pin descriptions host interface pins serial output (so) so is a push/pull serial data out put pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9401. chip select (cs ) when cs is high, the x9401 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9401, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 - a 1 ) the address inputs are used to set t he least significant 2 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9401. a maximum of 4 devices may occupy the spi serial bus. potentiometer pins v h (v h0 - v h3 )/ r h (r h0 - r h3 ), v l (v l0 - v l3 )/r l (r l0 - r l3 ) the v h /r h and v l /r l inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. vw (vw0 - vw3)/ rw (rw0 - rw3) the wiper outputs are equival ent to the wiper output of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the wiper counter registers. ordering information part number part marking v cc limits (v) potentiometer organization (k ) temp range (c) package pkg. dwg. # x9401ws24iz* (note 1) x9401ws zi 5 10% 10 -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9401ws24i x9401ws i -40 to +85 24 ld soic (300 mil) m24.3 x9401ws24z* (note 1) x9401ws z -40 to +85 24 ld soic (300 mil) m24.3 x9401wv24iz* (note 1) x9401wv zi -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9401wv24z* (note 1) x9401wv z -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9401ws24i-2.7* (note 2) x9401ws g 2.7 to 5.5 -40 to +85 24 ld soic (300 mil) m24.3 x9401ws24iz-2.7* (note) x9401ws zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9401ws24z-2.7* (note 1) x9401ws zf -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9401wv24-2.7 x9401wv f -40 to +85 24 ld tssop (4.4mm) mdp0044 x9401wv24iz-2.7* (note 1) x9401wv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9401wv24z-2.7* (note 1) x9401wv zf -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 *add ?t1? suffix for tape and reel. please refer to tb347 for details on reel specifications. notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. 2. not recommended for new designs. x9401
3 fn8190.4 october 13, 2009 pinouts x9401 (24 ld soic) top view x9401 (24 ld tssop) top view device description the x9401 is a highly integrat ed microcircuit incorporating four resistor arrays and thei r associated registers and counters and the serial interface logic providing direct communication between the host and the xdcp potentiometers. serial interface the x9401 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be co nnected together, since they have three state outp uts. this can help to reduce system pin count. array description the x9401 is comprised of four resistor arrays. each array contains 63 discrete resistiv e segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the six bits of the wcr are decoded to select, and enable, one of sixt y-four switches. wiper counter register (wcr) the x9401 contains four wiper counter registers, one for each xdcp potentiometer. the wcr is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-fo ur switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (s erial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register or global xfr data register instruct ions (parallel load); it can be modified one step at a time by the increment/decrement instruction. finally, it is loade d with the contents of its data register zero (r0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9401 is powered-down. although the register is autom atically loaded with the value in r 0 upon power-up, this may be different from the value present at power-down. the wiper position must be stored in r 0 to insure restoring the wiper position after power-up. pin descriptions soic pin # tssop pin # symbol description 523 cs chip select 17 11 sck serial clock 7, 19 1, 13 si, s0 serial data 20, 8 14, 2 a 0 - a 1 device address 3, 10, 15, 22, 2, 9, 16, 23 21, 4, 9, 16, 20, 3, 10, 17 v h0 /r h0, v h1 /r h1, v h2 /r h2 , v h3 /r h3 , v l0 /r l0, v l1 /r l1 , v l2 /r l2, v l3 /r l3 potentiometer end terminals 4, 11, 14, 21 22, 5, 8, 15 v w0 /r w0, v w1 /r w1, v w2 /r w2, v w3 /r w3 wipers 624 wp hardware write protection 18 12 hold hardware hold 119 v cc system supply voltage 12 6 v ss system ground 13, 24 7, 18 nc no connection 1 2 3 4 5 6 7 8 9 10 11 12 v cc v l0 /r l0 v h0 /r h0 v w0 /r w0 cs wp si a 1 v l1 /r l1 v h1 /r h1 v w1 /r w1 v ss 16 17 18 19 20 21 22 23 24 15 14 13 nc v h3 /r h3 v w3 /r w3 a 0 s0 sck v h2 /r h2 v w2 /r w2 nc v l3 /r l3 hold v l2 /r l2 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 si a 1 v l1 /r l1 v h1 /r h1 v w1 /r w1 v ss nc v w2 /r w2 v h2 /r h2 v l2 /r l2 sck hold wp v w0 /r w0 v h0 /r h0 v l0 /r l0 v cc v l3 /r l3 v w3 /r w3 a 0 s0 cs nc v h3 /r h3 x9401
4 fn8190.4 october 13, 2009 data registers each potentiometer has four 6- bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not re quire storage of multiple settings for the potentiometer, the data registers can be used as memory locations for system parameters or user preference data. data register detail write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions identification (id) byte the first byte sent to the x9401 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the slave address are a device type identifier. for the x9401 this is fixed as 0101[b] (refer to figure 1). the two least significant bits in the id byte select one of four devices on the bus. the physical device address is defined by the state of the a 0 - a 1 input pins. the x9401 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9401 to successfully continue the command sequence. the a 0 - a 1 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. instruction byte the next byte sent to the x9401 contains the instruction and register pointer information. the four most significant bits are the instruction. the next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. the format is shown below in figure 2. i the four high order bits of the instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits (p1 and p 0 ) selects which one of the four pot entiometers is to be affected by the instruction. four of the ten instructions ar e two bytes in length and end with the transmission of th e instruction byte. these instructions are: ? xfr data register to wiper counter register: this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter register to data register: this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data register to wiper counter register: this transfers the contents of all sp ecified data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register: this transfers the contents of all wiper counter registers to the specified associated data registers. the basic sequence of the two byte instructions is illustrated in figure 3. these two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram cont rolling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (curre nt wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four pot entiometers and one of its associated registers; or it may occur globally, where the transfer occurs between al l potentiometers and one associated register. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9401; either between the host and one of the data registers (msb) (lsb) d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv 1 00 00 a1a0 device type identifier device address 1 figure 1. identification byte format i1 i2 i3 i0 r1 r0 p1 p0 pot select instructions figure 2. identification byte format x9401
5 fn8190.4 october 13, 2009 or directly between the host and the wiper counter register. these instructions are: ? read wiper counter register : read the current wiper position of the selected pot, ? write wiper counter register : change current wiper position of the selected pot, ? read data register : read the contents of the selected data register; ? write data register : write a new value to the selected data register. ? read status : this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 4 and figure 5. the final command is increment/decrement. it is different from the other commands, because it?s length is indeterminate. once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustration of the sequence and timing for this operation are shown in figure 6 and figure 7. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input wiper counter register inc/dec logic up/dn clk modified scl up/dn v h /r h v l /r l v w /r w if wcr = 00[h] then v w /r w = v l /r l if wcr = 3f[h] then v w /r w = v h /r h 8 6 c o u n t e r d e c o d e (wcr) (one of four arrays) x9401
6 fn8190.4 october 13, 2009 010100a1a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs figure 3. two-byte command sequence 0 101 a1a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si 0 0 d5 d4 d3 d2 d1 d0 cs 00 figure 4. three-byte command sequence (write) 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si cs 00 s0 0 0 d5 d4 d3 d2 d1 d0 don?t care figure 5. three-byte command sequence (read) 0101 00a1a0 i3 i2 i1 i0 0 p1 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs figure 6. increment/decrement command sequence x9401
7 fn8190.4 october 13, 2009 table 1. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 1 0 0 1 0 0 p 1 p 0 read the contents of the wiper counter register pointed to by p 1 - p 0 write wiper counter register 1 0 1 0 0 0 p 1 p 0 write new value to the wiper counter register pointed to by p 1 - p 0 read data register 1 0 1 1 r 1 r 0 p 1 p 0 read the contents of the data register pointed to by p 1 - p 0 and r 1 - r 0 write data register 1 1 0 0 r 1 r 0 p 1 p 0 write new value to the data register pointed to by p 1 - p 0 and r 1 - r 0 xfr data register to wiper counter register 1101r 1 r 0 p 1 p 0 transfer the contents of the data register pointed to by r 1 - r 0 to the wiper counter register pointed to by p 1 - p 0 xfr wiper counter register to data register 1110r 1 r 0 p 1 p 0 transfer the contents of the wiper counter register pointed to by p 1 - p 0 to the register pointed to by r 1 - r 0 global xfr data register to wiper counter register 0001r 1 r 0 0 0 transfer the contents of the data registers pointed to by r 1 - r 0 of all four pots to their respective wiper counter register global xfr wiper counter register to data register 1000r 1 r 0 0 0 transfer the contents of all wiper counter registers to their respective data registers pointed to by r 1 - r 0 of all four pots increment/decrement wiper counter register 00100 0p 1 p 0 enable increment/decrement of the wiper counter register pointed to by p 1 - p 0 read status (wip bit) 0 1 0 1 0 0 0 1 read the status of the internal write cycle, by checking the wip bit. sck si v w /r w inc/dec cmd issued t wrid voltage out figure 7. increment/decrement timing limits x9401
8 fn8190.4 october 13, 2009 instruction format notes: 3. a1 ~ a0?: stands for the device addresses sent by the master. 4. wpx refers to wiper position data in the counter register 5. ?i?: stands for the increment operation, si held high during active sck phase (high). 6. ?d?: stands for the decrement operation, si held low during active sck phase (high). read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer data register (dr) to wiper counter register (wcr) transfer wiper counter register (wcr) to data register (dr) increment/decrement wiper counter register (wcr) global transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9401 on so) cs rising edge 010100a1 a0 1 0 0 1 00 p1 p000wp5wp4wp3wp2wp1wp0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 0 1 0 1 0 0 a1 a0 1 0 1 0 0 0 p1 p0 0 0 wp5 wp4 wp3 wp2 wp1 wp0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9401 on so) cs rising edge 010100a1a 01011r1r0p1p000wp5wp4wp3wp2wp1wp0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high- voltage write cycle 0 1 0 1 00a1a0 1 1 0 0 r1r0p1p000wp5wp4wp3wp2wp1wp0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 010100a1a0 1 1 0 1r1r0p1p0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 010100 a1 a0 1110r1r0p1p0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 0 1 0 1 0 0 a1 a0 0 0 1 0 x x p1 p0 i/d i/d . . . . i/d i/d cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100a1a00001r1r000 x9401
9 fn8190.4 october 13, 2009 global transfer wiper counter register (wcr) to data register (dr) read status cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 010100a1a01 0 0 0 r1 r000 cs falling edge device type identifier device addresses instruction opcode wiper addresses data byte (sent by x9401 on so) cs rising edge 010100a1 a0 0 1 0 1 00010000000 wip x9401
10 fn8190.4 october 13, 2009 power-up and down requirements the are no restrictions on the power-up or power-down conditions of v cc and the voltages applied to the poten- tiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc power-up spec is always in effect. absolute maximum rati ngs thermal information supply voltage (v cc limits) x9401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9401-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v voltage on sck, scl or any address input with respect to v ss : . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v = |(v h ?v l )| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v temperature under bias . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. analog specifications (over recommended operating conditions unless otherwise stated.) symbol parameter test condition min (note 10) typ max (note 10) unit r total end to end resistance tolerance -20 +20 % power rating +25c, each pot 50 mw i w wiper current -6 +6 ma r w wiper resistance i w = (v h - v l )/r total v cc = 5v 150 500 v term voltage on any v h or v l pin v ss v cc v noise ref: 1khz -120 dbv resolution 1.6 % absolute linearity (note 7) v w(n)(actual) - v w(n)(expected) -1 +1 mi (note 9) relative linearity (note 8) v w(n+1) - [v w(n) + mi] -0.2 +0.2 mi (note 9) temperature coefficient of r total v(r h ) = v cc , v(r l ) = v ss 300 ppm/c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitances see macro model 10/10/25 pf i al r h , r l , r w leakage current v in = v ss device is in stand-by mode. 0.1 10 a notes: 7. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 8. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 9. mi = rtot/63 or (v h - v l )/63, single pot. 10. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established b y characterization and are not production tested. x9401
11 fn8190.4 october 13, 2009 equivalent ac load circuit dc operating characteristics (over the recommended operating conditi ons unless otherwise specified.) symbol parameter test conditions min (note 10) typ max (note 10) unit i cc1 v cc supply current (active) f sck = 2mhz, so = open, other inputs = v ss 700 a i cc2 v cc supply current (non-volatile write) f sck = 2mhz, so = open, other inputs = v ss 3ma i sb v cc current (standby) sck = si = v ss , addr. = v ss , cs = v cc 3a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v cc +0.5 v v il input low voltage ?0.5 v cc x 0.1 v v ol output low voltage i ol = 3ma 0.4 v endurance and data retention parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol test typ. unit test condition c out (note 11) output capacitance (so) 8 pf v out = 0v c in (note 11) input capacitance (a0, a1, si, and sck) 6 pf v in = 0v power-up timing input pulse levels = v cc x 0.1 to v cc x 0.9; input rise and fall times = 10ns; input and output timing level = v cc x 0.5. symbol parameter min. max. unit tr vcc (note 11) v cc power-up rate 0.2 50 v/ms tpur (note 12) power-up to initiation of read operation 1 ms tpuw (note 12) power-up to initiation of write operation 5 ms notes: 11. this parameter is not 100% tested. 12. t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. 5v 1533 100pf sda output r h 10pf c l c l r w r total c w 25pf 10pf r l spice macro model x9401
12 fn8190.4 october 13, 2009 ac timing symbol parameter min. (note 10) max. (note 10) unit f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle rime 500 ns t wh ssi/spi clock high rime 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 150 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 20 ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns high-voltage write cycle timing symbol parameter typ max (note 10) unit t wr high-voltage write cycle time (store instructions) 5 10 ms xdcp timing symbol parameter min. max. (note 10) unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sc k edge (increment/decrement instruction) 450 ns x9401
13 fn8190.4 october 13, 2009 symbol table timing diagrams input timing output timing waveform inputs outputs must be steady will be steady may change from lo w to high will change from lo w to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... x9401
14 fn8190.4 october 13, 2009 hold timing xdcp timing (for all load instructions) xdcp timing (for increment/decrement instruction) write protect and device address pins timing ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo ... cs sck si msb lsb v w /r w t wrl ... so high impedance ... cs sck so si addr t wrid high impedance v w /r w ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction) x9401
15 fn8190.4 october 13, 2009 applications information basic configurations of electronic potentiometers application circuits v r v w /r w + v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysteresis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k +5v tl072 + ? v s v o r 2 r 1 } } attenuator filter + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) r 2 r 4 all r s = 10k + ? v s r 2 r 1 r c v o x9401
16 fn8190.4 october 13, 2009 application circuits (continued) inverting amplifier equivalent l-r circuit + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c x9401
17 fn8190.4 october 13, 2009 x9401 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8190.4 october 13, 2009 x9401 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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